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|
Title
|
Authors
|
Issue |
| Oscillator phase noise:
a tutorial |
Lee, T.H.; Hajimiri,
A.; |
MAR 2000
IEEE Xplore |
|
15 Refs
Linear time-invariant (LTI) phase noise theories provide important
qualitative design insights but are limited in their quantitative
predictive power. Part of the difficulty is that device noise
undergoes multiple frequency translations to become oscillator
phase noise. A quantitative understanding of this process requires
abandoning the principle of time invariance assumed in most
older theories of phase noise. Fortunately, the noise-to-phase
transfer function of oscillators is still linear, despite the
existence of the nonlinearities necessary for amplitude stabilization.
In addition to providing a quantitative reconciliation between
theory and measurement, the time-varying phase noise model presented
in this tutorial identifies the importance of symmetry in suppressing
the upconversion of 1/f noise into close-in phase noise, and
provides an explicit appreciation of cyclostationary effects
and AM-PM conversion. These insights allow a reinterpretation
of why the Colpitts oscillator exhibits good performance, and
suggest new oscillator topologies. Tuned LC and ring oscillator
circuit examples are presented to reinforce the theoretical
considerations developed. Simulation issues and the accommodation
of amplitude noise are considered in appendixes
|
| Technology developments
driving an evolution of cellular phone power amplifiers to integrated
RF front-end modules |
Jos, R |
|
11 Refs
Abstract: Millions of cellular phone power amplifiers (PAs) are
produced every day worldwide using a great diversity of technologies.
This is true both for the active devices, where various silicon
as well as GaAs transistors are used, and for the PA architecture,
in which MMIC, module, and discrete solutions compete. This paper
gives an overview of the various technological and architectural
choices and discusses their influence on the PA performance, notably
the power efficiency and linearity. It sketches the future of
PA development toward more functional integration, which may be
obtained by two paths: integration on chip and added functionality
in modules
|
| Monolithic transformers for silicon
RF IC design |
Long, J.R. |
Sep.2000
IEEE
Xplore
|
|
31 Refs
Abstract: The construction and electrical characteristics of
two-port transformers (1:1 and 1:n turns ratio) and multi-port
transformer baluns fabricated in a production silicon technology
are presented. A high-linearity 5 GHz mixer design illustrates
the advantages of the trifilar transformer in an RF IC application
|
Addition to "Development
of a GaAs monolithic surface acoustic
wave integrated circuit"
|
Baca. A.G.,Heller, E.J.,Casalnuovo,S.A.,Frye-Mason,
G.C., Klem, J.F., Drummond, T.J. |
Aug.2000
IEEE
Xplore
|
6 Refs
Abstract: An oscillator technology using surface acoustic wave
(SAW) delay lines integrated with GaAs MESFET electronics has
been developed for GaAs-based integrated microsensor ap- plications.
The oscillator consists of a two-port SAW delay line in a feedback
loop with a four-stage GaAs MESFET amplifier. Oscillators with
frequencies of 470, 350, and 200 MHz have been designed and fabricated.
This oscillator technology is most suitable for sensor applications
but can logically be extended to radio-frequency oscillator and
filter applications by methods well known for other piezoelectric
substrates. |
| Oscillator Phase Noise: A Tutorial |
Thomas H. Lee, Ali Hajimiri |
Mar 2000
IEEE
Xplore |
|
15 Refs
Abstract: Linear time-invariant (LTI) phase noise theories provide
important qualitative design insights but are limited in their
quantitative predictive power. Part of the difficulty is that
device noise undergoes multiple frequency translations to become
oscillator phase noise. A quantitative understanding of this
process requires abandoning the principle of time invariance
assumed in most older theories of phase noise. Fortunately,
the noise-to-phase transfer function of oscillators is still
linear, despite the existence of the nonlinearities necessary
for amplitude stabilization. In addition to providing a quantitative
reconciliation between theory and measurement, the time-varying
phase noise model presented in this tutorial identifies the
importance of symmetry in suppressing the upconversion of 1/f
noise into close-in phase noise, and provides an explicit appreciation
of cyclostationary effects and AM-PM conversion. These insights
allow a reinterpretation of why the Colpitts oscillator exhibits
good performance, and suggest new oscillator topologies. Tuned
LC and ring oscillator circuit examples are presented to reinforce
the theoretical considerations developed. Simulation issues
and the accommodation of amplitude noise are considered in appendixes
|
| Introduction to RF simulation
and its application |
Kundert, K.S. |
Sept. 1999
IEEE
Xplore |
|
68 Refs
Abstract: Radio-frequency (RF) circuits exhibit several distinguishing
characteristics that make them difficult to simulate using traditional
SPICE transient analysis. The various extensions to the harmonic
balance and shooting method simulation algorithms are able to
exploit these characteristics to provide rapid and accurate
simulation for these circuits. This paper is an introduction
to RF simulation methods and how they are applied to make common
RF measurements. It describes the unique characteristics of
RF circuits, the methods developed to simulate these circuits,
and the application of these methods
|
The state of the art of electrostatic
discharge protection: physics, technology, circuits, design, simulation,
and scaling
|
Voldman, S.H. |
Sept. 1999
IEEE
Xplore |
82 Refs
Abstract: This paper discusses state-of-the-art electrostatic
discharge (ESD) protection in advanced semiconductor technologies
and emerging technologies. ESD physics, semiconductor process
issues, device and circuit simulation, circuits, and devices are
examined |
| High-speed DRAM architecture development |
Ikeda, H., Inukai, H.
|
May 1999
IEEE
Xplore |
5 Refs
Abstract: This paper is an overview of the high-speed DRAM architecture
developments. We discuss developments on density growth, interface
technology, memory-core architecture, and DRAM+ASIC technology.
We can find the developments of density as 2× growth instead
of 4× by each generation. Interface technologies will have
a tendency to use the terminated bus structure for higher data
rate. Memory-core architecture developments are the trials for
actual bandwidth improvements. DRAM+ASIC technologies seem to
require universal interface solutions. We tried to show that no
single solution is able to cover the wide diversity of future
system requirements |
| CMOS technology-year 2010 and
beyond |
Iwai, H. |
March 1999
IEEE
Xplore |
25 Refs
Abstract: MOS large-scale-integration circuits (LSI's), having
advanced remarkably during the past 25 years, are expected to
continue to progress well into the next century. The progress
has been driven by the downsizing of the components in an LSI,
such as MOSFET's. However, even before the downsizing of MOS-
FET's reaches its fundamental limit, the downsizing is expected
to encounter severe technological and economic problems at the
beginning of next century when the minimum feature size of LSI's
is going to shift to 0.1 and sub-0.1 \mum. In this paper, the
anticipated difficulties and some concepts for 0.1- and sub-0.1-
\mum LSI's are explained based on the research of the downsizing
MOSFET into such a dimension, and a further concept for deep sub-0.1-\mum
LSI's is described. |
| Microwave CMOS-device physics
and design |
Manku, T. |
March 1999
IEEE
Xplore |
32 Refs
Abstract: This paper discusses design issues and the microwave
properties of CMOS devices. A qualitative understanding of the
microwave characteristics of MOS transistors is provided. The
paper is directed toward helping analog IC circuit designers create
better front end radio-frequency CMOS circuits. The network properties
of CMOS devices, the frequency response, and the microwave noise
properties are reviewed, and a summary of the microwave scaling
rules is presented |
| CMOS technology characterization
for analog and RF design |
Razavi, B. |
March 1999
IEEE
Xplore |
26 Refs
Abstract: The design of analog and radio-frequency (RF) circuits
in CMOS technology becomes increasingly more difficult as device
modeling faces new challenges in deep submicrometer processes
and emerging circuit applications. The sophisticated set of characteristics
used to represent today's “digital” technologies often
proves inadequate for analog and RF design, mandating many additional
measurements and iterations to arrive at an acceptable solution.
This paper describes a set of characterization vehicles that can
be employed to quantify the analog behaviour of active and passive
devices in CMOS processes, in particular, properties that are
not modeled accurately by SPICE parameters. Test structures and
circuits are introduced for measuring speed, noise, linearity,
loss, matching, and dc characteristics |
| Integrated circuit technology options for RFICs-present
status and future directions |
Larson, L.E. |
|
87 Refs
Abstract: This paper will summarize the technology tradeoffs that
are involved in the implementation of radio frequency integrated
circuits for wireless communications. Radio transceiver circuits
have a very broad range of requirements-including noise figure,
linearity, gain, phase noise, and power dissipation. The advantages
and disadvantages of each of the competing technologies-Si CMOS
and bipolar junction transistors (BJTs), Si/SiGe HBTs and GaAs
MESFETs, PHEMTS and HBTs will be examined in light of these requirements
|
The Multi-tanh Principle:
A Tutorial Overview
Barrie Gilbert
|
Barrie Gilbert |
Jan. 1998
IEEE
Xplore |
22 Refs
Abstract: This paper reviews a class of linear transconductance
cells, having proven value in a variety of communications applications,
characterized by the use of parallel- or series-connected sets
of differential pairs of bipolar transistors whose inputs and
outputs are connected in parallel. These cells invoke a well-developed
concept, known as the “multi-tanh principle”. The key
idea is that the individually nonlinear (hyperbolic tangent, or
tanh) transconductance functions may be separated along the input-voltage
axis to achieve a much more linear overall function. The simplest
of these is the so-called the “doublet”; the linearity
criterion and noise behavior are discussed in detail. Some novel
forms are presented. Higher order cells, including the “triplet”,
are then discussed, together with a novel method for achieving
linear-in-dB gain control with an important modification for extending
the dynamic range |
| A history of the invention
of the transistor and where it will lead us |
Brinkman, W.F., Haggan,
D.E., Troutman, W.W.
|
Dec. 1997
IEEE
Xplore |
11 Refs
Abstract Fifty years ago, in November 1947, John Bardeen and Walter
Brattain discovered the transistor on the fourth floor of Building
1 at Bell Labs in Murray Hill, NJ. Fifty years later, the authors
are still working with silicon but it is a very different silicon
effort. Currently with the silicon optical bench they are trying
to integrate optical components the way transistors have been
over the last 50 years. So, silicon technology is still progressing.
When considering the invention of the transistor, the authors
note that the work of Bardeen and Brattain was really a discovery
not an invention. At the time they discovered transistor action,
they were investigating the nature of surface states and ways
to reduce their presence. It was only later that things really
became clear as to what was going on. Fifty years later that discovery
is celebrated, and the authors present a brief history of the
major events and the key people involved |
| Energy dissipation in general
purpose microprocessors |
Gonzalez, R, Horowitz,M. |
Sept. 1996
IEEE
Xplore |
19 Refs
Abstract: In this paper we investigate possible ways to improve
the energy efficiency of a general purpose microprocessor. We
show that the energy of a processor depends on its performance,
so we chose the energy-delay product to compare different processors.
To improve the energy-delay product we explore methods of reducing
energy consumption that do not lead to performance loss (i.e.
wasted energy), and explore methods to reduce delay by exploiting
instruction level parallelism. We found that careful design reduced
the energy dissipation by almost 25%. Pipelining can give approximately
a 2× improvement in energy-delay product. Superscalar issue,
however, does not improve the energy-delay product any further
since the overhead required offsets the gains in performance.
Further improvements will be hard to come by since a large fraction
of the energy (50-80%) is dissipated in the clock network and
the on-chip memories. Thus, the efficiency of processors will
depend more on the technology being used and the algorithm chosen
by the programmer than the micro-architecture |
| Direct-conversion radio transceivers
for digital communications |
Abidi, A.A. |
Dec. 1995
IEEE
Xplore |
51 Refs
Abstract: The current interest in portable wireless communications
devices is prompting research into new IC technologies, circuit
configurations, and transceiver architectures. Miniature transceivers
dissipating low power are sought to sought to communicate digital
data. While transistor technology scaling and improved circuit
techniques will lead to the inevitable evolutionary advances towards
this goal, architectural innovations in the transceiver will lead
to revolutionary improvements. It is in this context that there
is a resurgence of interest in direct-conversion |
| Applications for GaAs and silicon
integrated circuits in next generation wireless communication
systems |
Burns, L.M. |
Oct. 1995
IEEE
Xplore |
14 Refs
Abstract: Emerging applications for portable wireless voice and
data communications systems are requiring increased data rates
and functionality. Meeting cost and performance goals requires
careful attention to system level design and partitioning such
that appropriate technologies are employed in cost-effective solutions.
New circuit designs and techniques are required to meet size,
power, and regulatory restrictions. This provides an exciting
opportunity for GaAs, silicon, and passive component technologies.
This review paper will discuss factors influencing the choice
of which technology is best suited to a particular application
and present several system level architectures of radio-based
communication systems. The paper will illustrate appropriate applications
of GaAs, silicon, and passive integrated circuit technologies.
A summary is given that highlights the relative strengths and
weaknesses of each technology to date |
| Present and future directions
for multichip module technologies |
Sudo, T. |
April 1995
IEEE
Xplore |
|
21 Refs
Abstract: Multichip modules (MCM's) have been actively developed
in recent years. They are expected to provide high-performance
systems by packing bare chips at a high density. In particular,
a thin-film interconnect substrate that can accommodate higher
wiring capacity in a few layers is a new option for coping with
high pin count and fine pad pitch VLSI's. MCM's require various
kinds of technologies including the fabrication processes of
interconnect substrates, chip connection methods, electrical
design, thermal management, known good die (KGD), and so on.
The state of the art of MCM technologies is reviewed and future
directions are discussed.
|
| Future directions in microprocessor
technology |
Marks, M.P |
April 1995
IEEE
Xplore |
6 Refs
Abstract: The application trends and key design tradeoffs involved
in the design of high performance microprocessors are discussed.
In particular the growing importance of improved human interface
technology and the need for high-performance, highly-connected
systems combined with the need to continue to drive costs lower
make design choices very difficult. Technical innovation in the
areas of high bandwidth processor-memory interfaces, low-cost
multiprocessors and software compatibility are needed in order
to continue move forward |
| Evolution of high-speed operational amplifier
architectures |
Smith, D. |
Oct. 1994
IEEE
Xplore |
14 Refs
Abstract: Strengths and weaknesses of modern wide-bandwidth bipolar
transistor operational amplifiers are investigated and compared
with respect to bandwidth, slew rate, noise, distortion, and power.
This paper traces the evolution of operational amplifier designs
since vacuum tube days to give a perspective of the large number
of circuit variations used over time. Of particular value is the
ability to use many of these circuit design options as the basis
of new amplifiers. In addition, an array of operational amplifier
components fabricated on the AT&T CBIC V2 process is described.
This design incorporates many of the architectural techniques
that have evolved over the years to produce four separate operational
amplifier on a single base wafer. The process design methodology
requires identifying the common elements in each architecture
and the minimum number of additional components required to implement
four unique architectures on the array |
| Integrated continuous-time filter design -
an overview |
Tsividis, Y.P. |
March 1994
IEEE
Xplore |
66 Refs
Abstract: The state of the art of continuous-time filter design
is reviewed. Several techniques are discussed and compared in
terms of performance and implementation feasibility in different
fabrication technologies. This review does not aim at historical
completeness, but rather emphasizes techniques that have proven
their worth in commercial applications. Brief mention is also
made of experimental work which, in the opinion of the author,
shows promise for the future |
| Current-mode CMOS multiple-valued
logic circuits |
Current, K.W. |
Feb. 1994 pp 95-107
IEEE
Xplore |
32 Refs
Abstract: Current-mode CMOS circuits are receiving increasing
attention. Current-mode CMOS multiple-valued logic circuits are
interesting and may have applications in digital signal processing
and computing. In this paper we review several of the current-mode
CMOS multiple-valued logic (MVL) circuits that we have studied
over the past decade. These circuits include a simple current
threshold comparator, current-mode MVL encoders and decoders,
current-mode quaternary threshold logic full adders (QFAs), current-mode
MVL latches, current-mode latched QFA circuits, and current-mode
analog-to-quaternary converter circuits. Each of these circuits
is presented and its performance described |
| MOS Operational Amplifier Design-
A Tutorial Overview |
Gray, Paul R., Meyer, Robert G. |
Dec. 1982
IEEE
Xplore |
30 Refs
Abstract: This paper presents an overview of current design techniques
for operational amplifiers implemented in CMOS and NMOS technology
at a tutorial level. Primary emphasis is placed on CMOS amplifiers
because of their more widespread use. Factors affecting voltage
gain, input noise, offsets, common mode and power supply rejection,
power dissipation, and transient response are considered for the
traditional bipolar-derived two-stage architecture. Alternative
circuit approaches for optimization of particular performance
aspects are summarized, and examples are given. |
| Design Considerations Analog Integrated
in Single-Channel MOS Circuits --A Tutorial |
Tsividis, Yannius P. |
June 1978
IEEE
Xplore |
18 Refs
Abstract: The design of single-channel MOS analog integrated circuits
is discussed. Simple models axe presented and approximate design
equations are given for basic analog cells. The emphasis is on
first-order analysis as a starting point for computer-aided design.
|
| The Monolithic Op Amp: A Tutorial
Study |
Solomon, James E. |
Dec. 1974
IEEE
Xplore |
13 Refs
Abstract: A study is made of the integrated circuit operational
amplifier (IC op amp) to explain details of its behavior in a
simplified and understandable manner. Included are analyses of
thermal feedback effects on gain, basic relationships for bandwidth
and slew rate, and a discussion of pole-splitting frequency compensation.
Sources of second-order bandlimiting in the amplifier are also
identified and some approaches to speed and bandwidth improvement
are developed. Brief sections are included on new JFET-bipolar
circuitry and die area reduction techniques using transconductance
reduction. |
