SESSION
MP 5
SALON
9,
Mon.,
7
1:30
PM
HIGH-FREQUENCY
MICROPROCESSORS
Chair:
D. Greenhill, Sun Microsystems, Palo Alto, CA
Associate
Chair: D. Bearden, Motorola Inc., Austin, TX
5.1 A
1GHz Alpha Microprocessor
1:30
PM
B.
Benschneider, S. Park
2,
R. Allmon, W. Anderson, M. Arneborn,
J.
Cho
1,
C. Choi
1,
J. Clouser, S. Han
1,
R. Hokinson, G. Hwang
1,
D.
Jung
1,
Ji. Kim
1,
Ja. Kim
1,
M. Kim
1,
K. Koo
1,
J. Krause, J. Kwack
1,
J.
Lee
1,
S. Meier, Y. Seok
2,
S. Thierauf, J. White, C. Zhou
2
Compaq
Computer Corp., Shrewsbury, MA
1Samsung
Electronics Corp., Seoul, Korea
2Alpha
Processor Inc., Boxboro, MA
An
air-cooled Alpha microprocessor with an internal clock frequency >1GHz uses
1.5V 0.18
um
CMOS with 7 aluminum interconnect layers and dissipates 65W. The circuit
challenges to scale to these performance levels are discussed.
5.2 A
660MHz 64b SOI Processor with Cu Interconnects
2:00
PM
T.
Buchholtz, A. Aipperspach, D. Cox, N. Phan, S. Storino, J. Strom, R. Williams
IBM
Corp., Rochester, MN
A
660MHz 64b PowerPC processor in 0.18
um
SOI copper technology has a 20% frequency gain over a design in a 0.22
um
SOI technology. A SOI body-controlled buffer has 18% delay reduction. Adaptive
techniques adjust for changes in I/O level, L2 bus timing, and stress condition
testing.
5.3 A
780MHz PowerPC Microprocessor with Integrated L2 Cache
2:30
PM
D.
Bearden, D. Caffo, P. Anderson, P. Rossbach, N. Iyengar,
T.
Petersen, J.-T. Yen
Motorola
Somerset Design Center, Austin, TX
This
processor implements the PowerPC architecture incorporating AltiVec. Using 0.18
um
1.5V CMOS with 6 layers of copper interconnect, it operates up to 780MHz. The
105mm
2
chip contains a 256kB L2 cache, tags for up to 2MB of L3, and two 32kB L1
caches. The 64b bus and cache interfaces support 2.5V or 1.8V operation.
BREAK 3:00
PM
5.4 A
1GHz Single-Issue 64b PowerPC Processor 3:15 PM
H.
Hofstee, N. Aoki, D. Boerstler, P. Coulman
1,
S. Dhong, B. Flachs, N. Kojima, O. Kwon, K. Lee, D. Meltzer
2,
K. Nowka, J. Park, J. Peter, S. Posluszny, M. Shapiro
3,
J. Silberman
2,
O. Takahashi,
B.
Weinberger
IBM
Austin Research Lab, Austin, TX
1IBM
Server Development, Austin, TX
2IBM
T. J. Watson Research Ctr., Yorktown Heights, NY
3IBM
Microelectronics, Austin, TX
A
single-issue short-pipe 1GHz PowerPC processor uses 0.22
um
(0.12
um
L
eff),
6-level copper interconnect CMOS. The design uses nearly 100% dynamic circuits
and includes 64kB caches, address translation hardware, and dual precision
low-latency floating point unit.
5.5 A
600MHz PA-RISC Microprocessor
3:45 PM
K.
Hurd
Hewlett
Packard Co., Fort Collins, CO
The
PA-RISC microprocessor is highly leveraged from a previous implementation with
1.2x performance increase goals in the same 0.25
um
process using clock cycle reduction and improved performance per clock cycle.
One key to accomplishing this goal is a LRU cache for the 1MB dual-ported data
cache.
5.6 760MHz
G6 S/390 Microprocessor Exploiting Multiple Vt and Copper Interconnects
4:15 PM
T.
McPherson, R. Averill, D. Balazich, K. Barkley, S. Carey, Y. Chan, Y. H. Chan,
R. Crea, A. Dansky, R. Dwyer, A. Haen
1,
D. Hoffman,
A.
Jatkowski, M. Mayo, D. Merrill, T. McNamara, G. Northrop,
1,
J.
Rawlins, L. Sigal
1,
T. Slegel, D. Webber, P. Williams, F. Yee
1
IBM
Server Development, Poughkeepsie, NY
1IBM
Research Div., Yorktown Heights, NY
A
microprocessor in 0.22
um
(0.12
um
L
eff)
CMOS operates at 760MHz in an S/390 G6 Enterprise Server. 27% frequency
improvement over the G5 processor is achieved from technology scaling, copper
interconnect, and multiple device thresholds. Low-V
T
devices provide 10% of the performance improvement and are implemented using an
automated methodology. The G6 ships at 637MHz in a chilled 12+2 SMP sytem.
5.7 A
1GHz IA-32 Microprocessor Implemented on 0.18
um
Technology with Aluminum Interconnect
4:45 PM
P.
Green
Intel
Corp., Hillsboro, OR
A
25M+ transistor 0.18
um
CMOS, 6-layer aluminum interconnect processor operates at 1GHz at room
temperature. Performance is achieved by a combination of interconnect aspect
ratio optimization, low-K dielectric and design timing optimization.
Incremental design effort is low compared to the same design with copper
interconnect.
CONCLUSION 5:15
PM