The analog design community faces new challenges of requirements for analog front-end building blocks such as high-voltage high-performance high-efficiency line drivers, high-resolution high-speed a/d and d/a converters, and upstream/downstream filters.

The major success of DSL technology worldwide places all telecom manufacturers under pressure for next-generation DSL products: increasing density of the lines per board, reducing power consumption per line and maximising loop reach and robustness against disturbances such as RFI and bridge taps.

DMT signalling has opened golden gates on copper cable but leaves the system with a power bottleneck in the line drivers because of the high crest factor. Class A/B amplifiers, still in ADSL production lines, will soon be replaced with Class G, Class H, Class K and other high-efficiency power amplifier concepts re-invented today, going back to the future and remembering audio low-power high-efficiency concepts.

Loop-reach requirement push analog designers to achieve 14b-resolution a/d and d/a converters in high-volume-production highly-integrated analog front ends. Sigma-delta pipelined and various subranging architectures at the interface between analog and digital are revisited in advanced research programs. FDM upstream/downstream filtering is reconsidered to avoid carrier attenuation in the filter overlap region and the consequent loss of loop reach.

Speakers from telecom and silicon industry and from university research centers bring attendees up to date on the analog challenges of this emerging access application.

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